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nonvolati l e, i 2 c compatible 64-position, digital potentiometer preliminary technical data ad5258 rev. prh 7/22/04 | page 1 of 14 information furnished by analog devices is believed to be accurate and reliable. how ever, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise u nder a ny patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703? 2004 analog devices, inc. all rights reserved. fea t ures nonvolatile me moy maintains wiper settings 64-position compact msop-10 ( 3 mm 4. 9 mm) package i 2 c? compatibl e interface v logi c pin provides increase d i n terface flexibi l ity. end-to-end r e s istance 1 k?, 1 0 k?, 50 k?, 10 0 k? resistance tole rance stored in eemem(0.1% a ccuracy) power on eemem refresh ti me < 1m s software write protect comma nd tri-state addr e ss deco de pins ad0 and ad1 100-y ear t y pical dat a retenti o n at 55c wide operatin g temperature C40c to + 85c +3v to +5v sin gle-supply a pplic a t io ns lcd panel v com adjustm e nt lcd panel brig htness and contrast control mechanical pot e ntiometer replacement in ne w designs programmable power supplies rf amplifier bi asing automotive e l ectronics adjustment gain control and offset a d just ment low resolution dac replacem ent electronics level settings gener a l ov er view the ad5258 p r o v ides a com p ac t n o n v ol a t ile 3 mm 4.9 mm pa c k a g ed so l u tio n f o r 6 4 - pos i ti o n a d j u s t m e n t a p p l i c a t i o n s . t h ese de v i ce s p e rf o r m th e sa m e e l ectr o n i c ad j u s t m e n t fun c ti o n as m e c h anic al p o t e n t iomet e rs or va r i a b le r e sis t o r s, wi t h e n h a n c ed r e so l u ti o n a n d so l i d-s t a t e r e li a b il i t y . the wi p e r s e t t i n gs a r e co n t r o l l a b l e t h r o ug h a n i 2 c co m p a t i b le dig i tal in t e r f ace , which can als o be us e d t o r e ad bac k t h e wi p e r re g i ste r and e e m e m c o n t e n t. r e s i stor tol e r a nc e is a l s o store d wi t h i n eemem a nd can b e us e d to p r o v ide an end-to -e n d toler a n c e ac c u r a c y o f 0.1%. i n o r der to p r o v id e adde d s e c u r i t y , co mman d b i t s ar e a v a i la b l e t o place t h e p a r t in to a wr i t e p r o t e c t m o de i n w h ich d a t a ca n n o t b e wr i t te n to t h e e e mem r e g i ster . in a d d i t i o n , a s e p a r a t e v lo g i c p i n p r o v ides t h e u s er w i t h i n cr eased i n t e rfa c e f l e x i b ili t y . f o r use r s wh o n eed m u l t i p l e p a r t s o n o n e b u s, addr ess b i ts a d 0 a nd a d 1 a l l o w u p to ni ne de vices on t h e s a m e b u s. func ti onal bl oc k di a g rams da t a cont rol rdac eep ro m co m m a n d de c o de l o g i c add res s dec o de l o g i c co nt ro l l o g i c r dac 1 re g i s t e r a1 w1 b1 r dac 1 sc l sd a i2c ser i al i n ter fa ce ad 0 vdd vl og i c 8 powe r on r e se t 8 dgnd ad 1 fi g u r e 1 . fi g u r e 3 . p i n o u t . note: the terms di gital potentiometer , vr , and rdac are use d inte rchange a bl y. purc hase of l i c e nse d i 2 c c o mp on ent s of a n al og devi c e s o r on e of i t s sub l i c ensed associated c o mpani e s conv eys a license f o r the purcha ser un d e r the philips i 2 c paten t rig h ts to use th ese co mpon en ts in an i 2 c system , provi d ed th at the system co n f o r ms to th e i 2 c stan d a r d s p ecificatio n as d e fin e d by p h ilips. 1 2 3 4 5 10 9 8 7 6 w ad0 ad1 sda scl a d 5 258 to p v i e w ( n ot t o scale) a b vdd g n d vlogic
ad5258 prelim inary technical data rev. pr h 7/22/04 | page 2 of 14 table of contents e l ec tr ical cha r ac t e r i s t ics?1 k , 10 k, 50 k, 100 k ve r s i o n s .............................................................................................. 3 t i min g cha r ac ter i s t ics?1 k, 10 k, 50 k, 1 00 k v e rsio n s 4 ab s o l u t e m a x i m u m r a t i n g s 1 .......................................................... 5 o u t l i n e d i me ns i o ns ....................................................................... 12 or der i n g g u ide .......................................................................... 13 es d c a u t io n ................................................................................ 13 revisi on h i s t or y re vision 0: i n i t ial v e rsio n i 2 c ser i a l in t e r f a c e scl sd a ad 0 ad 1 v dd gnd a w b a d 5258 vl ogi c rd a c reg i st er and level sh ift e r eeprom co mm a n d decode l ogic a ddress decode l ogic cont rol lo gic f i gu r e 3. bl ock d i agr a m sh o w i n g leve l shif ters
ad5258 preliminary technical data rev. prh 7/22/04 | page 3 of 14 electrical characteristics?1 k, 10 k, 50 k, 100 k versions (v dd = 5 v 10%, or 3 v 10%; v a = v dd ; v b = 0 v; ?40c < t a < +85c; unless otherwise noted.) table 1. parameter symbol conditions min ma nit dc caracteristicsreostat mode resistor differential nonlinearity r-dnl r w a no connect 1 0.1 1 ls resistor integral nonlinearity r-inl r w a no connect 2 0.25 2 ls nominal resistor tolerance r a t a 25c 30 30 resistance temperature coefficient r a /t a dd wiper no connect 650 ppm/c r w r w code 000 50 120 dc caracteristicspotentiometer diider mode differential nonlinearity dnl 1 0.1 1 ls integral nonlinearity inl 1 0.3 1 ls oltage divider temperature coefficient w /t code 020 30 ppm/c full-scale error wfse code 0ff 3 1 0 ls ero-scale error wse code 000 0 1 3 ls resistor terminals oltage range aw ss dd capacitance a c a f 1 m measured to gnd code 020 45 pf capacitance w c w f 1 m measured to gnd code 020 60 pf common-mode leakage i cm a dd /2 1 na digital inpts and otpts input logic igh i 0.7 l l 0.5 input logic low il 0.5 0.3 l input current i il in 0 or 5 1 a input capacitance c il 5 pf power spplies power supply range dd 2.7 5.5 positive supply current i dd i 5 or il 0 1 a logic supply(must match logic levels) logic 2.7 dd programming mo de current(eemem) i logic(prog) i 5 or il 0 35 ma power dissipation p diss i 5 or il 0 dd 5 18 50 w power supply sensitivity pss dd 5 10 code midscale 0.02 0.05 / dnamic caracteristics andwidth 3d w r a 1k/ 10 k/50 k/100 k code 020 10000/600/ 100/40 k total armonic distortion td w a 1 rms 0 f 1 k r a 10 k 0.1 w settling time (1k/10 k/50 k/100 k) t s a 5 0 1 ls error band 2 s resistor noise oltage density e nw r w 5 k rs 0 9 n/
ad5258 prelim inary technical data rev. pr h 7/22/04 | page 4 of 14 timing characteristics?1 k, 10 k, 50 k, 100 k versions (v dd = +5v 10% , o r +3v 10% ; v a = v dd ; v b = 0 v ; ?40c < t a < + 8 5 c ; u n l e ss ot he r w i s e no te d. ) table 2. p a r a m e t e r s y m b o l c o n d i t i o n s m i n t y p m a n i t i 2 c inte rface timing c arac teris t ics 1 (specifications apply to all parts) scl clock freu ency f scl 0 4 0 0 k t f us free time between stop and start t 1 1 . 3 s t dsta old time (repeated sta r t) t 2 after this period the first clock p u lse is generated. 0 . 6 s t low low period of scl clock t 3 1 . 3 s t ig igh period of scl clock t 4 0 . 6 s t s st a setup tim e for repeated start condition t 5 0 . 6 s t ddat data old time t 6 0 0 . 9 s t s dat data setu p time t 7 1 0 0 n s t f fall time of oth sda and sc l signals t 8 3 0 0 n s t r rise time of oth sda and sc l signals t 9 3 0 0 n s t s st o setup tim e for stop condition t 10 0 . 6 s t 1 scl sda ps p 0 3842-0-003 t 3 t 2 t 8 t 9 t 8 t 9 t 4 t 5 t 7 t 6 t 10 fi g u r e 4 . i 2 c i n t e r f ac e timing d i agr a m
ad5258 preliminary technical data rev. pr h 7/22/04 | page 5 of 14 i 2 c interface table 3. generi c interface for m at s device address* (7-bit) r/w sa c2 c1 c0 a4 a3 a2 a1 a0 sa d5 d4 d3 d2 d1 d0 sa p slave address yte instruction yte data yte table 4. de vice ad dress look up* (note that ad1 and ad0 are tri-sta t e ad d r es s p i n s ) dev i ce a ddr ess 0 01100 0 0 0 0 01100 1 n c 0 0 01101 0 1 0 0 10100 1 0 nc 0 10101 0 n c n c 0 10101 1 1 nc 1 00110 0 0 1 1 00110 1 n c 1 1 00111 0 1 1 ad 1 a d 0 s s t a r t c o ndi t i o n p s t o p c o nd i t io n sa sla v e a c k n o w le dg e ma m a s t er a c kn o w le dge na n o a c k n o w l e d g e d o n t c a r e w w r i t e r re ad table 5. rdac -to-eemem inte rface comma nd descriptions c 2 c 1 c 0 c o mmand des c ri p t i o n 0 0 0 operation between i 2 c and rdac 0 0 1 operation between i 2 c and eeprom 0 1 0 operation between i 2 c and wp register 1 0 0 nop 1 0 1 restore eeprom to rdac 1 1 0 store rda c to eeprom
ad5258 preliminary technical data rev. prh 7/22/04 | page 6 of 14 write modes table 6. writing to rdac register s device address* (7-bit) 0 sa 0 0 0 0 0 0 0 0 sa d5 d4 d3 d2 d1 d0 sa p slave address yte instruction yte data yte table 7. writing to eeprom register s device address* (7-bit) 0 sa 0 0 1 0 0 0 0 0 sa d5 d4 d3 d2 d1 d0 sa p slave address yte instruction yte data yte table 8. activating software write protect s device address* (7-bit) 0 sa 0 1 0 0 0 0 0 0 sa 0 0 0 0 0 0 0 wp sa p slave address yte instruction yte data yte store/restore modes table 9. storing rdac value to eeprom s device address* (7-bit) 0 sa 1 1 0 0 0 0 0 0 sa p slave address yte instruction yte table 10. restoring eeprom to rdac s device address* (7-bit) 0 sa 1 0 1 0 0 0 0 0 sa p slave address yte instruction yte s start condition p stop condition sa slave acknowledge ma master acknowledge na no acknowledge dont care w write r read
ad5258 preliminary technical data rev. prh 7/22/04 | page 7 of 14 read modes table 11. traditional read back of rdac register value s device address* (7-bit) 0 sa 0 0 0 0 0 0 0 0 sa s device address* (7-bit) 1 sa x x d5 d4 d3 d2 d1 d0 na p slave address byte instruction byte slave address byte read back data repeat start table 12. traditional read back of stored eeprom value s device address* (7-bit) 0 sa 0 0 1 0 0 0 0 0 sa s device address* (7-bit) 1 sa x x d5 d4 d3 d2 d1 d0 na p slave address byte instruction byte slave address byte read back data repeat start table 13. traditional read back of tolerance i. consecutively s device address (7-bit) 0 sa 0 0 1 1 1 1 1 0 sa s device address (7-bit) 1 sa d7 d6 d5 d4 d3 d2 d1 d 0 ma d7 d6 d5 d4 d3 d2 d1 d0 na p slave address byte instruction byte slave address byte sign + integer byte decimal byte repeat start ii. individually s device address* (7-bit) 0 sa 0 0 1 1 1 1 1 0 sa s device address* (7-bit) 1 sa d7 d6 d5 d4 d3 d2 d1 d 0 na p slave address byte instruction byte slave address byte sign + integer byte repeat start s device address* (7-bit) 0 sa 0 0 1 1 1 1 1 1 sa s device address* (7-bit) 1 sa d7 d6 d5 d4 d3 d2 d1 d 0 na p slave address byte instruction byte slave address byte decimal byte repeat start note: read modes above are referred to as traditional because the first two bytes for all three cases are dummy bytes which function to place the pointer towards the correct register. this is the reason for the repeat start. in theory, this step can be avoided if the user is interested in reading a register that was previously written to. for example, if the eeprom was just written to, then the user can skip the
ad5258 prelim inary technical data rev. pr h 7/22/04 | page 8 of 14 tw o d u m m y b y tes a nd p r o c e e d dir e c t ly to t h e ? s la ve a d dr ess by te ? w h ich w o u l d b e fol l o w e d b y t h e ? r e a d b a ck d a t a ? . calculating r ab tolerance stored in read-only memory -- aa d7 d6 d5 d4 d3 d2 d1 d0 sign sign 7 bits for integer number 2 6 2 5 2 4 2 3 2 2 2 1 2 0 a d7 d6 d5 d4 d3 d2 d1 d0 8 bits for decimal number 2 ?8 2 ?1 2 ?2 2 ?3 2 ?4 2 ?5 2 ?6 2 ?7 f i gure 5 . f o rm a t o f st or ed t o l e r a nce i n si gn m a gni t ud e f o rma t wi th bi t p o si t i o n descri ptio ns . (u ni t i s per cent. o n l y da ta b y tes ar e sh own.) te a e a t ur e a a t e n t e d r ab t o lera n c e t o r a g e i n t e no n ol a t i l e m e mo r y t e t o lerance i t o r e d in t e m e m o r y d u r i n g ac t o r y r o d uc t i o n and ca n e r e ad y u er a t an y t i me t e k n o w le dg e o t o r e d t o lera n c e al lo w u er t o calc u l a t e r ab acc u ra t e ly ti e a t ur e i a l u a le o r r e c iio n re o t a t m o de and o e n -lo o a lic a t i o n w er e k n o w le dge o a o lu t e r e it an ce i cr i t ica l te t o r e d t o lera n c e r e i de i n t e r e ad-o nl y mem o r y an d i e r e e d a a e rcen t a g e te t o l e ra n c e i t o r e d in tw o m e m o r y l oc a t i o n in ig n ma g n i t u d e i na r y o r m ee i gur e t e tw o eemem addr e y t e ar e ig n in t eg er an d decimal n u m er t e tw o y te can e acce e d i ndi i d u a l ly in tw o e a r a te co mm an d e e t a l e ii a l ter n a t i ely i n o r der to a l lo w r e ad a ck o t e i r t y t e ol l o w e d y t e e co nd y te in on e command e e t a l e i t e m e m o r y o in t e r w i l l a u to ma t i c a l l y in cr e m e n t r o m t e i r t to t e e co nd eeme m lo ca tion in c r em en t r o m t o i r e ad co n ec u t i e l y n t e i rt m e m o r y lo ca t i on t e ms b i deig n a t e d o r t e ig n a n d a nd t e sb a r e deig n a t e d o r t e i n teg e r o r t i o n o t e toler a n c e n t e e cond mem o r y lo ca t i on a l l eig t da t a i t a r e deig n a t e d o r t e de c i m a l o r t io n o toler a n c e o r e a m l e i t e ra t e d r ab k a n d t e da ta r e ad ack r o m a ddr e o w a nd a d dr e o w t en t e tolera n c e ca n e calc u l a t e d a ms b e t ms b s b t o lera n c e an d t er eo r e r aba ct a k eemem write-acknowledg e polling a t e r e a c wr i t e o era t io n t o t e eemem r e g i t er a n i n ter n al wr i t e c y cle e g i n t e c in t e r ace o t e de i ce i di a l e d t o det e r m i n e i t e in t e r n a l wr i t e c y cle i co m let e a nd t e c in ter ace i ena le d in t e r ac e o l l i n g can e ee c u t e d c in t e r ace o l l in g ca n e cond uc te d y e n d in g a t a r t co ndi t i o n ol l o w e d y t e la e addr e t e wr i t e i t t e c in t e r ace r e o n d w i t an a c t e wr i t e c y cle i co m let e and t e i n t e r ac e i r e ady t o r o c e e d w i t u r t e r o era t io n o t e r - wi e c in t e r a c e o ll i n g c a n e r e ea t ed un til i t u cceed
ad5258 preliminary technical data rev. prh 7/22/04 | page 9 of 14 i 2 c compatible 2-wire serial bus 1. the master initiates data transfer by establishing a start condition, which is when a high-to-low transition on the sda line occurs while scl is high (see figure 4). the following byte is the slave address byte, which consists of the slave address followed by an r/ w bit (this bit determines whether data is read from or written to the slave device). the ad5258 has two tri-state configurable address bits, ad0 and ad1 (see table 4). the slave whose address corresponds to the transmitted address responds by pulling the sda line low during the ninth clock pulse (this is termed the acknowledge bit). at this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. if the r/ w bit is high, the master reads from the slave device. if the r/ w bit is low, the master writes to the slave device. 2. writing: in the write mode, the last bit(r/ w ) of the address byte is logic low. the second byte is the instruction byte. the first 3 bits of the instruction byte are the command bits(see table 5). the final 5 bits indicate which eemem location the pointer moves to. the user must choose whether to write to the rdac register, eemem register, or activate the software write protect(see tables 6-8). the final byte is the data byte msb first. in the case of the write protect mode, data is not being stored. rather, a logic high in the lsb will enable write protect and a logic low will disable write protect. 3. storing/restoring: in this mode, only two bytes are necessary; address and instruction bytes. the last bit (r/ w ) of the address byte is logic low. the first 3 bits of the instruction byte are the command bits(see table 5). the two choices are transfer data from rdac to eemem(store) or from eemem to rdac(restore). the final 5 bits are all zeros(see tables 9-10). 4. reading: assuming the register of interest was not just written to, it is necessary to write a dummy address and instruction byte. the instruction byte will vary depending on whether the data that is wanted is the rdac register, eemem register, or tolerance register(see tables 11-13). the tolerance register can be read back consecutively(table 13i) or individually(table13ii). refer to page 8 for detailed information on the interpretation of the tolerance bytes. after the dummy address and instruction bytes are sent, a repeat start is necessary. after the repeat start, another address byte is needed except this time, the r/ w bit is logic high . following this address byte is the read back byte containing the information requested in the instruction byte. 5. after all data bits have been read or written, a stop condition is established by the master. a stop condition is defined as a low-to-high transition on the sda line while scl is high. in write mode, the master pulls the sda line high during the 10 th clock pulse to establish a stop condition (see figure 6). in read mode, the master issues a no acknowledge for the ninth clock pulse (i.e., the sda line remains high). the master then brings the sda line low before the 10 th clock pulse, and then raises sda high to establish a stop condition (see figure 7). a repeated write function gives the user flexibility to update the rdac output a number of times after addressing and instructing the part only once. for example, after the rdac has acknowledged its slave address and instruction bytes in the write mode, the rdac output is updated on each successive byte. if different instructions are needed, the write/read mode has to start again with a new slave address, instruction, and data byte. similarly, a repeated read function of the rdac is also allowed.
ad5258 prelim inary technical data rev. pr h 7/22/04 | page 10 of 14 display applications f i gur e 1. v co m adj u st me n t a p pl ic a t ion as su mi ng t h a t a + 5 v sup p ly is a v ai l a bl e . i n t h is c a s e , v dd and v lo g i c wou l d b e t i e d to ge t h e r . f i gur e 2. this c i r c ui t de m o n s t r a t es t h e f l exib i l i t y o f a v lo g i c pi n w h e n a s e p a r a te s u pp l y i s not a v ai l a bl e f o r v dd . v dd ca n b e ta p p ed o f f t h e +14.4 v w h e r e i t is r e sisto r d i vi de d do w n to a p p r o x im a t ely ~5v . v lo g i c ca n th en be tak e n o f f th e sa m e s u p p l y th a t po w e r s th e m c u ? s log i c lev e l s. n o w , t h e 35 ma p r og ra mmin g c u r r en t wil l b e dr a w n b y v lo g i c , a nd v dd wi l l on ly dr a w mic r o a m p s of su p p ly c u r r e n t u s e d to b i as u p t h e i n t e r n al sw i t ch es in t h e dig i t a l p o t e n t io met e r ? s in ter n al r e sis t o r s t r i n g .
ad5258 preliminary technical data rev. prh 7/22/04 | page 11 of 14 absolute maximum ratings 1 (t a = +25c, unless otherwise noted.) table 4 parameter alue dd to gnd 0.3 to 7 a w to gnd ss 0.3 dd 0.3 i ma pulsed 1 continuous 20 ma 5 ma digital inputs and output o ltage to gnd 0 to 7 operating temperature range 40c to 85c maimum unction temperature (t ma ) 150c storage temperature 65c to 150c lead temperature (soldering 10 sec) 300c thermal resistance 2 a : msop-10 200c/w notes 1 maimum terminal current is bounde d by the maimum current handling of the switches maimum power dissip ation of the package and maimum applied voltage across any two of the a and w terminals at a given resistance. 2 package power dissipation (t ma t a )/ a . stresses above those listed under absolute maimum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. eposure to absolute maimum rating conditions for etended periods may affect device reliability.
ad5258 prelim inary technical data rev. pr h 7/22/04 | page 12 of 14 pin conf iguration and fu nction descriptions f i g u re 2. a d 51 72 p i n conf ig ur at io n ta ble 5. a d 52 5 pi n f u nct i o n d e s c ri pt i o ns p i n m n e m o n i c d e s c r i p t i o n 1 terminal. d v v dd . 2 ado programmable tri-state ad dress bit 0 for multip le package decoding. 3 ad1 programmable tri-state ad dress bit 1 for multip le package decoding. 4 sda serial data inpu t output. 5 scl serial clock input. positive edg e triggered. v l o i c logic p o w e r s u p p l y . 7 d d i g i t a l r o u n d . vdd positive power s u pply. b b terminal. d v b v dd . 10 a a terminal. d v a v dd . 1 2 3 4 5 10 7 ad 0 ad 1 sda sc l a d 5 25 to p v i (ot to s c a l e ) a b v d d d vloic
ad5258 preliminary technical data rev. pr h 7/22/04 | page 13 of 14 outlin e dimen s ion s 0.23 0.20 0.17 0.80 0.40 8 0 0.15 0.00 0.27 0.17 0.95 0.85 0.75 seating plane 1.10 ma x 10 6 5 1 0.50 bsc 3.00 bsc 3 .00 bsc 4.90 bsc pin 1 compliant to jedec standards mo-187ba coplanarity 0.10 f i g u re 3. 10-l e a d m i ni sm a ll o u t lin e p a ckag e [ m s o p ] (r m - 10) di me nsio ns sho w n i n mi ll im e t e r s ordri uid m o d e l r ab () temperature package descri ption package option branding ad525brm1 1 1k 40c to 5c msop-10 rm-10 d4 ad525brm1- rl7 1 1k 40c to 5c msop-10 rm-10 d4 ad525brm10 1 10k 40c to 5c msop-10 rm-10 d4l ad525brm10 -rl7 1 10k 40c to 5c msop-10 rm-10 d4l ad525brm50 1 50k 40c to 5c msop-10 rm-10 d4m ad525brm50 -rl7 1 50k 40c to 5c msop-10 rm-10 d4m ad525brm10 0 1 100k 40c to 5c msop-10 rm-10 d4 ad525brm10 0-rl7 1 100k 40c to 5c msop-10 rm-10 d4 1 pb-f r e e p a r t . sd cautio sd (electrostatic discharge) sensitive device. le c trosta tic charg e s as high as 4000 v readily accumulate on the human body and test e uipment and can discharge with out detection. although this product features proprietary sd protection circu i try permanent dama ge may occur on devices subected to high energy electrostatic discharges. theref ore prop er sd precautions a r e recommended to avoid perform a nce degradation or l o ss of functiona l ity.
ad5258 prelim inary technical data rev. pr h 7/22/04 | page 14 of 14 notes ? 2003 analo g de vices, inc. all rights reserve d . tra d em arks and registered tra d emar ks are the proper ty o f th eir respectiv e c o mpan ies . pr05029C0C7/04(p r h)

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